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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:35:51 10/15/2008 
-- Design Name: 
-- Module Name:    uartklok - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity uartklok is
    Port ( clk : in  STD_LOGIC;
           uart_klok : out  STD_LOGIC);
end uartklok;

architecture Behavioral of uartklok is
signal tel : integer range 0 to 31 := 0;
begin
process(clk)
begin
  if rising_edge(clk) then
   if tel = 26 then --tel = 26  voor 115200
	    tel <= 0;
		 uart_klok <= '1';
   else
	    tel <= tel + 1;
		 uart_klok <= '0';
	end if;
  end if;
end process;

end Behavioral;

